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| Ordering number : EN4795C CMOS LSI LC321664AJ, AM, AT-80 1 MEG (65536 words x 16 bits) DRAM Fast Page Mode, Byte Write Overview The LC321664AJ, AM, AT is a CMOS dynamic RAM operating on a single 5 V power source and having a 65536-word x 16-bit configuration. Equipped with large capacity capabilities, high-speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in compact plastic packages of SOJ 40-pin, SOP 40-pin and TSOP 44-pin. Refresh rates are within 4 ms with 256 row address (A0 to A7) selection and support RAS-only refresh, CAS-before-RAS refresh and hidden refresh settings. There are functions such as page mode, read-modifywrite, and byte-write. Package Dimensions unit: mm 3200-SOJ40 [LC321664AJ] Features * * * * * * * * 65536-word x 16-bit configuration Single 5 V 10% power supply All input and output (I/O) TTL compatible Supports fast page mode, read-modify-write, and bytewrite. Supports output caching control using early write and Output Enable (OE) control. 4 ms refresh using 256 refresh cycles Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh. Packages SOJ 40-pin (400 mil) plastic package: LC321664AJ SOP 40-pin (525 mil) plastic package: LC321664AM TSOP 44-pin (400 mil) plastic package: LC321664AT RAS access time/column address access time/CAS access time/ cycle time/power dissipation SANYO:SOJ40 unit : mm 3195-SOP40 [LC321664AM] * SANYO:SOP40 Parameter RAS access time Column address access time CAS access time Cycle time Power dissipation (max.) During operation During standby LC321664AJ, AM, AT-80 80 ns 45 ns 30 ns 135 ns 633 mW 5.5 mW (CMOS level)/11 mW (TTL level) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 32896HA (OT)/O3194TH/81094TH (OT) No. 4795-1/30 LC321664AJ, AM, AT-80 Package Dimensions unit : mm 3207-TSOP44 [LC321664AT] SANYO:TSOP44 (TYPE-II) Pin Assignments No. 4795-2/30 LC321664AJ, AM, AT-80 Block Diagram Specifications Absolute Maximum Ratings Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Output short-circuit current Operating temperature range Storage temperature range LC321664AJ, AM LC321664AT Symbol VCC max VIN VOUT Pd max IOUT Topr Tstg Ratings -1.0 to +7.0 -1.0 to +7.0 -1.0 to +7.0 800 700 Unit V V V mW mA C C Note 1 1 1 1 1 1 1 50 0 to +70 -55 to +150 Note: 1) Stresses greater than the above listed maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70C Parameter Power supply voltage Input high level voltage Input low level voltage (A0 to A7, RAS, CAS, UW, LW, OE) Input low level voltage (I/O1 to I/O16) Symbol VCC VIH VIL VIL min 4.5 2.4 -1.0* -0.5* typ 5.0 max 5.5 6.5 +0.8 +0.8 Unit V V V V Note 2 2 2 2 Note: 2) All voltages are referenced to VSS. A bypass capacitor of about 0.1 F should be connected between VCC and VSS of the device. * -2.0 V when pulse width is less than 20 ns No. 4795-3/30 LC321664AJ, AM, AT-80 DC Electrical Characteristics at Ta = 0 to + 70C, VCC = 5 V 10% Parameter Operating current (Average current during operation) Standby current RAS-only refresh current Fast page mode current Standby current CAS-before-RAS refresh current Input leakage current Output leakage current Output high level voltage Output low level voltage Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 IIL IOL VOH VOL Conditions RAS, CAS, address cycling: tRC = tRC min RAS = CAS = VIH RAS cycling, CAS = VIH: tRC = tRC min RAS = VIL, CAS address cycling: tPC = tPC min RAS = CAS = VCC-0.2V RAS, CAS cycling: tRC = tRC min 0V VIN 6.5V, pins other than measuring pin = 0V DOUT disable, 0V VOUT 5.5V IOUT = -2.5mA IOUT = 2.1mA -10 -10 2.4 0.4 min max 115 2 115 70 1 115 +10 +10 Unit mA mA mA mA mA mA A A V V 3 3, 5 3, 4, 5 Note 3, 4, 5 Note: 3) All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here value becomes smaller. Note: 4) ICC1 and ICC4 are dependent on output loads. Maximum values for ICC1 and ICC4 represent values with output open. Note: 5) One address change can be performed while RAS = VIL (ICC1 and ICC3). One address change can be performed during one tPC cycle (ICC4). No. 4795-4/30 LC321664AJ, AM, AT-80 AC Electrical Characteristics at Ta = 0 to +70C, VCC = 5 V 10% (Note 6, 7, 8) Parameter Random read or write cycle time Read-write/read-modify-write cycle time Fast page mode cycle time Fast page mode Read-write/read-modifywrite cycle time RAS access time CAS access time Column address access time CAS precharge access time Output low-impedance time from CAS low Output buffer turn-off delay time Rise or fall time RAS precharge time RAS pulse width RAS pulse width for fast page mode only RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time Column address hold time referenced to RAS Column address to RAS lead time Read command setup time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command hold time referenced to RAS Write command pulse width Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tCLZ tOFF tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP 0 0 3 45 80 80 30 80 30 25 17 10 10 0 12 0 20 60 45 0 0 0 15 60 15 10000 50 35 10000 100000 20 50 min 135 180 55 100 80 30 45 50 max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 14 15 9, 14 15 9, 14 9, 15 9 9 10 Note Continued on next page. No. 4795-5/30 LC321664AJ, AM, AT-80 Continued from preceding page. Parameter Write command to RAS lead time Write command to CAS lead time Data input setup time Data input hold time Data input hold time referenced to RAS Refresh period Write command setup time CAS to UW, LW delay time RAS to UW, LW delay time Column address to UW, LW delay time CAS precharge to UW, LW delay time (fast page mode cycle only) Symbol tRWL tCWL tDS tDH tDHR tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tROH tOEA tOED tOEZ tOEH tDZC tDZO tMCS tMRH tMCH min 20 20 0 20 60 max Unit ns ns ns ns ns Note 12 12 4 0 50 100 65 70 10 15 10 40 15 25 15 0 20 0 0 0 0 0 15 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 16 10 9 13 13 13 13 13 CAS setup time for CAS-before-RAS refresh CAS hold time for CAS-before-RAS refresh RAS precharge time to CAS active time CAS precharge time for CAS-before-RAS counter test RAS hold time referenced to OE OE access time OE delay time OE to output buffer turn-off delay time OE command hold time Data input to CAS delay time Data input to OE delay time Masked write setup time Masked write hold time referenced to RAS Masked write hold time referenced to CAS Input/Output Capacitance at Ta = 25C, f = 1 MHz, VCC = 5 V 10% Parameter Input capacitance (A0 to A7, RAS, CAS, UW, LW, OE) I/O capacitance (I/O1 to I/O16) Symbol CIN CI/O min max 7 7 Unit pF pF No. 4795-6/30 LC321664AJ, AM, AT-80 Notes: 6) After the power is turned on, 200 s are required after the arrival of VCC stabilized current before memory is initialized and begins operation. In addition, before memory operation initializes, approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the RAS dummy cycles. Measured at tT = 5 ns. When measuring input signal timing, VIH (min) and VIL (max) are used for reference points. In addition, rise and fall time are defined between VIH and VIL. Measured using an equivalent of 50 pF and one standard TTL load. 7) 8) 9) 10) tOFF (max) and tOEZ (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11) Operation is guaranteed if either tRRH or tRCH are satisfied. 12) These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a read-write/read-modify-write cycle. 13) tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters for memory in that they specify the operating mode. If tWCS tWCS (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. If tCWD tCWD (min), tRWD tRWD (min), tAWD tAWD (min) and tCPWD tCPWD (min), the cycle switches to a read-write/read-modify-write cycle and data outputs equal information in the selected cells. If neither of the above conditions are satisfied, output pins are in an undefined state. 14) tRCD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRCD tRCD (max), access time is determined according to tCAC. 15) tRAD (max) does not indicate a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRAD tRAD (max), access time is determined according to tAA. 16) Operation is guaranteed if either tDZC or tDZO are satisfied. No. 4795-7/30 LC321664AJ, AM, AT-80 Timing Chart Read Cycle No. 4795-8/30 LC321664AJ, AM, AT-80 Early Write Cycle No. 4795-9/30 LC321664AJ, AM, AT-80 Upper Byte Early Write Cycle No. 4795-10/30 LC321664AJ, AM, AT-80 Lower Byte Early Write Cycle No. 4795-11/30 LC321664AJ, AM, AT-80 Write Cycle (OE Control) No. 4795-12/30 LC321664AJ, AM, AT-80 Upper Byte Write Cycle (OE Control) No. 4795-13/30 LC321664AJ, AM, AT-80 Lower Byte Write Cycle (OE Control) No. 4795-14/30 LC321664AJ, AM, AT-80 Read-Modify-Write Cycle No. 4795-15/30 LC321664AJ, AM, AT-80 Read-Modify Upper Byte Write Cycle No. 4795-16/30 LC321664AJ, AM, AT-80 Read-Modify Lower Byte Write Cycle No. 4795-17/30 LC321664AJ, AM, AT-80 Fast Page Mode Read Cycle No. 4795-18/30 LC321664AJ, AM, AT-80 Fast Page Mode Early Write Cycle No. 4795-19/30 LC321664AJ, AM, AT-80 Fast Page Mode Upper Byte Early Write Cycle No. 4795-20/30 LC321664AJ, AM, AT-80 Fast Page Mode Lower Byte Early Write Cycle No. 4795-21/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify-Write Cycle No. 4795-22/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify Upper Byte Write Cycle No. 4795-23/30 LC321664AJ, AM, AT-80 Fast Page Mode Read-Modify Lower Byte Write Cycle No. 4795-24/30 LC321664AJ, AM, AT-80 Hidden Refresh Cycle No. 4795-25/30 LC321664AJ, AM, AT-80 RAS-Only Refresh Cycle CAS-Before-RAS Refresh Cycle No. 4795-26/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (read) No. 4795-27/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (write) No. 4795-28/30 LC321664AJ, AM, AT-80 CAS-Before-RAS Refresh Counter Test Cycle (read-modify-write) No. 4795-29/30 LC321664AJ, AM, AT-80 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March 1996. Specifications and information herein are subject to change without notice. PS No. 4795-30/30 |
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